In the conventional computer systems, a CPU local bus which is connected with a CPU and main memory or the like and an I/O bus connected with an I/O interface have been connected with a bus bridge. In such a conventional computer system, a large scale system hardware structure has not yet been realized, and one CPU local bus has principally been connected to one I/O interface, namely on the basis of the 1:1 relationship for the interface bridged with a bus bridge.
Thereafter, in a computer system, such as a server which is required to assure particularly higher processing capability like basic business processes in enterprises, the processing capability has been improved by interconnecting a plurality of processors. This is accomplished by realizing a structure of the large scale SMP (Symmetrical Multi-Processor) type. In the computer system of such a large scale SMP structure, the connecting structure provides a relationship of n:1 or n:m (n, m: natural number) of one I/O interface or a plurality of I/O interfaces for one I/O interface, or a plurality of I/O interfaces for a plurality of CPU local buses has been required. Accordingly, the conventional bus bridge has been replaced with a crossbar switch and a system controller for supporting a plurality of interfaces. In the crossbar switches or the like, there has been provided a storage structure including a data queue for a plurality of input interfaces.
However, the method for providing a data queue for every group of input interfaces is not effective because the number of data queues such as buffers, FIFOs, or RAMs increases as the number of input interfaces increases and the results in a problem in the development of crossbar switches or the like to realize a computer system of larger scale.
FIG. 5 illustrates an example of a conventional data queue controlling apparatus including a plurality of input interfaces of an identical type. The data queue controlling apparatus of FIG. 5 includes, as the input interface, the interfaces IF0 to IF4 of the identical type. The apparatus receives the packet data 511 of a 4-byte width outputted from the other Large Scale Integrations (LSIs) and output IF 5 as an input interface.
The packet data 511 of the 4-byte width inputted to each interface of IF0 to IF4 is coupled to the packet data of an 8-byte width in which the even number packet data and following odd number packet data are arranged with buffers 521 to 525. The coupled packet data of 8-byte width is queued to the RAMs 531 to 535 of 8-byte width forming a data queue. The packet data of 8-byte width queued to the RAMs 531 to 535 are converted again to two packet data of 4-byte width with conversion buffers 541 to 545.
The converted packet data of 4-byte width is respectively inputted to the inputs IN0 to IN4 of a multiplexer 561. The packet data inputted to the multiplexer 561 is selected with a priority controller 551 and thereby outputted to the IF 5. At the IF 5, the priority controller 551 determines priority, such as IN0→IN1→IN2→IN3→IN4→IN1.
As described above, the conventional data queue controlling apparatus has controlled the queuing of packet data by providing a data queue corresponding to the input interface on a 1:1 basis. However, the amount of input of packet data from each input interface has not always been uniform, and therefore, loading the data queue corresponding to each input interface on a 1:1 basis has not yet been effectively performed.
Japanese patent publication No. 3452424 relates to a common buffer memory controlling apparatus, such as an ATM switching apparatus. The publication particularly discloses a common buffer memory controlling apparatus which is suitable for message communication services for transferring one message data consisting of a plurality of cells. Japanese patent publication No. 3452424 discloses a common buffer memory controlling apparatus for storing message data via separation into a plurality of cells within the common buffer memory, which is formed of a single buffer memory as the data queue. However, Japanese patent publication No. 3452424 discloses technology for storing all message data into the buffer memory as the identical data queue. Thus, the effective queuing method of packet data for certain data queues formed of a number which is less than the number of input interfaces is not disclosed in the patent document.
Because the data queue of a buffer or a RAM of a large capacity requires a larger area, manufacturing yield of semiconductors is lowered. In addition, a logical amount of address decoders becomes large. Thus, for example, it is sometimes preferential, from the viewpoint of yield of LSI, operating frequency, and power consumption thereof, to form the data queue of a constant amount by utilizing the data queues of a plurality of buffers or RAMs of an intermediate capacity rather than to form only one buffer or RAM of the larger capacity. In addition, such a data queue becomes inferior to the data queue of a buffer or a RAM of the intermediate capacity in operation frequency and power consumption. The terms large capacity and intermediate capacity do not indicate a quantitative concept but rather a relative concept, which is determined by the amount of packet data inputted to the data queue controlling apparatus and the progress of semiconductor technology.
Japanese patent publication No. 3452424 does not disclose an effective method of controlling data queues.